At the 2026 IEEE International Symposium on Circuits and Systems (ISCAS), He Tingbo from HUAWEI gave a keynote speech called “New Semiconductor Path in Practice.” She introduced the Tau (τ) Scaling Law, which suggests using time (τ) scaling instead of geometric scaling to guide the future of the semiconductor industry. This approach allows for innovative technologies like LogicFolding to reduce signal propagation delays and increase transistor density, driving the advancement of semiconductors and electronic systems.
In recent years, Moore’s Law, which has been a guide for the semiconductor industry for over fifty years, is hitting serious limits. The global industry is facing challenges due to the slowing down of how small transistors can get and the decrease in cost benefits for each transistor. Now, the industry needs to find new ways to move forward that can meet the increasing demand for computing. This is where the τ Scaling Law becomes important.
Using this law, HUAWEI has created new technologies like LogicFolding and developed a system that helps improve semiconductor devices, circuits, chips, and systems together. This system aims to reduce the time constant τ to boost performance, energy efficiency, and how many transistors can fit at each level in the following ways:
- At the device level: Optimizing the resistance and parasitic capacitance of transistors and interconnects to minimize the device-level time constant τ at the underlying physical layer
- At the circuit level: Adopting the LogicFolding architecture to break down the physical boundaries of traditional circuit layouts, significantly shortening critical-path wiring, effectively reducing the resistive and capacitive load of signal propagation, and ultimately boosting transistor density and circuit performance
- At the chip level: Employing full-stack coordinated design of software, architecture, and silicon to achieve fine-grained, workload-driven control over instruction and data flows, enhancing system-level parallelism and efficiency, and significantly reducing end-to-end execution time
- At the system level: Redefining interconnect protocols for computing systems with UnifiedBus to achieve unified memory addressing and native memory semantics for SuperPoDs, significantly reducing system communications latency
In her keynote speech, He Tingbo discussed how HUAWEI uses the τ Scaling Law in smartphones and AI computing. In the last six years, HUAWEI has created 381 chips based on this law for various industries and markets. The Kirin chips set to launch in Fall 2026 will be the first to use the LogicFolding architecture, which will greatly improve their performance. By 2031, HUAWEI’s high-end chips based on the τ Scaling Law are anticipated to have a transistor density similar to 14 Å (1.4 nm) processes.
Looking ahead, He Tingbo noted, “We believe that openness and collaboration are key to driving ongoing progress in the semiconductor industry. No single company can independently find all the answers along the path of semiconductor evolution. With the τ Scaling Law, we look forward to working closely with scientists, engineers, and industry partners around the world to drive the sustainable development of the semiconductor and electronics industries.”